1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, it relates to a semiconductor device comprising a transistor element having quick response.
2. Prior Art
With the increase in degree of integration, still finer semiconductor elements for heavily integrated semiconductor devices are actively developed. MOS (metal-oxide-semiconductor) devices, which are dominant at present, are generally fabricated through process steps illustrated in FIG. 14.
[Process step 10]
Referring to FIG. 14(A), an element isolation region 12 is formed on a semiconductor substrate 10. Then, a gate contact area comprising an oxide film 14 and a polysilicon layer 24 is established on the surface of the semiconductor substrate 10.
[Process step 20]
Referring to FIG. 14(B), an LDD (lightly doped drain) structure is obtained by forming a side wall 34 on the side wall of the polysilicon layer 24 after establishing lightly doped shallow source.drain areas. Source.drain areas 36 are established by further subjecting the structure to ion implantation.
[Process step 30]
In the step illustrated in FIG. 14(C), an interlevel insulator layer 40 is formed, followed by providing an opening 42 therein, and by further establishing a connection layer 44.
Semiconductor devices are currently fabricated by a process comprising steps as described above. Recently, however, transistor elements operating at a higher speed are desired because of, for example, the demand for a further increased integration of logic circuits. AMOS transistor element with higher switching rate can be implemented by (A) shortening the channel length, and (B) increasing carrier mobility in the channel region.
A shorter channel length can be realized only with a progress in the technology of lithography. The formation of a fine resist pattern is requisite for a fine gate, i.e., a channel with a very short length. The minimum pattern length attainable at present in a process for mass production is about 0.5 .mu.m.
Furthermore, the so-called short channel effect becomes apparent with decreasing channel length. This effect results in the failure of attaining a desired threshold voltage, which further leads to problems such as an increase of power consumption and an unattainment of the expected characteristics as a transistor element. Moreover, when the short channel effect is particularly intense, punch thorough occurs that it becomes impossible to control of the current with gate voltage.
Recently, a method which comprises establishing SiGe in the base region is proposed as a means for increasing mobility of a Si-based transistor. It is generally accepted that the mobility of Ge is higher than that of Si. Accordingly, the formation of SiGe in the base region of a bipolar transistor increases the switching speed of the transistor. A method which comprises forming SiGe in the channel of a PMOS transistor for increasing the speed of the transistor is disclosed in V. P. Kensan, et al., "High Performance 0.25 .mu.m p-MOSFETs with Silicon-Germanium Channels for 300K and 77K Operation", International Electron Device Meeting (IEDM) 1991, Technical Digest pp. 25.
However, a drastic increase in the operation speed of a transistor cannot be expected even when an SiGe channel is incorporated. The average velocity v of the carriers which are involved in electric conduction is given by EQU v=.mu.E=.mu.IR
where .mu. represents mobility, E is electric field, I is current, and R is resistance. Considering that the mobility of Ge is 3,900 as compared to 1,500 of Si, the increase in average velocity which can be expected by replacing Si by Ge is merely about 2.6 times the conventional value.
At present, SiGe channel is deposited using CVD epitaxial growth technology. However, when a junction of Si and Ge is formed, rectifying characteristics is lost because a valence band barrier is formed due to the difference in band gap between Si and SiGe (for reference, see G. L. Patton, et al., "SiGe-BASE HETEROJUNCTION BIPOLAR TRANSISTORS:PHYSICS AND DESIGN ISSUES", IEDM 1990, Technical Digest 2.1.1-2.1.4). Accordingly, a technique for controlling the band gap by adjusting the concentration of Ge in Si is required for overcoming this problem. In a CVD process, however, it is extremely difficult to precisely control the concentration of Ge in Si.
An object of the present invention is, therefore, to provide a semiconductor device having stable characteristics and a further improved operation speed, which can be easily fabricated by applying a conventional process for fabricating MOS transistors without carrying out complicated fabrication steps.